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GP214D 1.4GHz DUAL PLL
DESCRIPTION
The GP214D is a dual frequency synthesizer designed for RF operation up to 1.4GHz. The device contains prescalers, programmable reference, and feedback frequency dividers, phase detectors, and charge pumps necessary for the precision control of dual VCO loops. Data transfer is made via a simple serial data interface. The GP214D is fabricated using advanced CMOS process and available in a 16-pin TSSOP plastic package with 0.65mm pitch.
FEATURES
Two systems for transmitter and receiver 2.4V to 5.0V operation (100MHz to 1.4GHz) Low current consumption 8.5mA @ 3.0V (Typ.) Modulus prescaler, 64 / 66 Selectable charge pump current 0.2mA, 0.4mA, 0.8mA, 1.6mA
Pb
16TSSOP
APPLICATIONS
Portable wireless communications (PCS, cordless) Other wireless communication systems
BLOCK DIAGRAM
Version 1.2 (Jan. 2006)
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GP214D 1.4GHz DUAL PLL
PIN DESCRIPTION
Pin No. 1 2, 15 3 4, 13 5 6 7 8 9 10 11 12 14 16
Symbol Fin1 Vcc CP1 GND LD CK DATA EN BO OSCO OSCI SW CP2 Fin2 RF input, channel 1.
Function Description
I/O I O O I O O I O O I
Power supply. Two pins are connected each other. Charge pump output, channel 1. Charge pump current is selected by the input serial data. Ground. Two pins are connected. Output of lock detection. It is the open drain output. Clock input. Serial data input. Input of enable signal. Serial data interface.
Output of buffer amplifier. The local signal passes through the buffer amplifier. Oscillator output. PLL reference input. Typically connected to a TCXO output. Switchover terminal to control time constant of loop filter. It is the open drain output. When switched off, it's normal output. Charge pump output, channel 2. RF input, channel 2.
ABSOLUTE MAXIMUM RATINGS
Parameters Power supply voltage Operating temperature Storage temperature ESD (Human body model) Symbol Vcc TOPR TSTG Value 5.5 -30 to +85 -35 to +150 2000 Unit V C C V
Note: This device is ESD sensitive. Appropriate ESD protection is required for device handling and assembly.
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GP214D 1.4GHz DUAL PLL
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, Vcc = 3.0V, Ta = 25C)
Characteristic Operating power supply voltage Operating current consumption Standby current Fin operating frequency Symbol Vcc Icc ISB Fin Test Condition Fin1= Fin2= 200MHz~1.4GHz Fin1= Fin2= 800MHz/ -5dBm input Standby mode Fin1=Fin2= -5dBm Vcc = 2.4V Fin1= Fin2= 200~1200MHz Fin input sensitivity Fin Vcc = 2.4V Fin1= Fin2= 1200~1400MHz Vcc = 3.0V Vcc = 5.0V OSCI operating frequency OSCI input voltage FOSC VOSC FOSC= 10~40MHz Serial data input high voltage (CK, DATA, EN) Serial data input low voltage (CK, DATA, EN) VIH Vcc= 1.7 to 5.0V 0.2 VIL ICP1 Charge pump output current ICP2 ICP3 ICP4 Charge pump leakage ICPL Vcc= 1.7 to 5.0V CP1= 0, CP2= 0 (VCP= 1/2 Vcc) CP1= 1, CP2= 0 (VCP= 1/2 Vcc) CP1= 0, CP2= 1 (VCP= 1/2 Vcc) CP1= 1, CP2= 1 (VCP= 1/2 Vcc) Standby mode (VCP= 1/2 Vcc) - 15% - 15% - 15% - 15% -1 0 1.6 0.2 0.4 0.8 0.2 + 15% + 15% mA +15% +15% 1 A V Vcc= 2.4~5.0V -15 Vcc - Vcc V 0 20 VFin= 0dBm, sinewave FOSC= 4~10MHz Vcc= 2.4~3.7V -15 -15 -15 4 -10 0 0 0 0 40 10 dBm MHz Vcc = 3.0V Vcc = 5.0V Min. 2.4 7.0 200 -15 -15 -15 Typ. 3.0 8.5 0 Max. 5.0 14.5 80 1400 10 10 10 dBm Unit V mA A MHz
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GP214D 1.4GHz DUAL PLL
PROGRAMMING DESCRIPTION
SERIAL DATA INPUT AND TIMING The programmable functions are accessed through the MCU serial data interface. The interface includes clock (CK, pin 6), data (DATA, pin 7) and enable signal (EN, pin 8). Serial data controls programmable reference counter and programmable counters in channel 1 and channel 2. The serial data is clocked in on the rising edge of clock and transferred into the shift register composed of 17-bit data field and 2-bit control field. When EN is high, stored data is latched. Data is entered LSB first.
A 0.1us
A 0.2us
A 0.2us
CK
LSB DATA N1(R1) N2(R2) A 0.1us A 0.2us N17(R12) GC2 MSB GC1 A 0.1us A 0.2us A 0.2us
EN
GROUP CODE AND LOCATION The data stored in the shift register is loaded into one of four appropriate latches depending on the state of group code (control bits) listed below.
Control Bits Data Location GC2(MSB-1) 0 1 0 1 GC1(MSB) 0 0 1 1 Control Latch Ch 1 N Latch Ch 2 N Latch OSC R Latch
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GP214D 1.4GHz DUAL PLL
OPTIONAL CONTROL The control register enables various functions shown in the table below.
LSB Bit1 T
Test Mode
Channel 1 Bit2 CP
Charge Pump Polarity
Channel 2 Bit5 SB1 Bit6 CP1 Bit7 CP2 Bit8 SB2
Ch2 Standby
MSB Bit9 SBR
Ref. Divider Standby
Bit3 CP1
Bit4 CP2
Bit10 LD1
Bit11 LD2
Bit12 SW
Filter Switch
Bit13 GC2
Bit14 GC1
Charge Pump Output Current
Ch 1 Standby
Charge Pump Output Current
Lock Detector
Group Code "0", "0"
Test mode selection (T) H: test mode, L: normal mode
Output polarity of charge pump (CP) CP is set to "0" at normal and changed to "1" when reverse operation, according to the dependence of VCO output frequency upon VCO input voltage. "Normal" denotes proportional response in the frequency to the VCO input voltage. Charge pump output current (CP1 and CP2) Charge pump employs circuits characterized by constant output current. The output current can be selected for the best performance.
Control Bits CP1 0 0 1 1 CP2 0 1 0 1
Charge Pump Output Current 1600A 200A 400A 800A
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GP214D 1.4GHz DUAL PLL
Test mode and lock detector output (T, LD1 and LD2)
The LD state can be changed via controlling SB1, SB2, LD1 and LD2.
T SB1 SB2 LD1 0 0 0 1 1 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 1 1 1 0 0 1 0 1 1 0 1 0 0 1 1 1 1 0 1 0 0 1 fpll1 fosc/2 low low 1 pres1 0 1 0 fpll2 fref div4 0 1 0 1 high high low pres2 0 1 low high 0 1 high channel2 0 1 low channel2 0 1 channel1 channel1 0 1 low high 0 1 channel1 channel 1 and channel2 LD2 0 1 LD Output State low channel2
x x
x x
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GP214D 1.4GHz DUAL PLL
Lock detector output
When the phase difference is detected, LD (pin 5) goes "L". When locked or at standby, LD changes to H". In case where the time difference, "T" less than 2/fosc (T<2/fosc) continues for more than three cycles of reference counter output, LD goes "H".
Fosc: OSCI operating frequency (LOCAL OSC) T: time difference of the pulse between reference divider output and channel divider output
Number of divisions by reference dividers fosc 2 B= fosc A=
A Reference Divider Output Channel Divider Output B
T Charge pump Output T<2/fosc
Lock Detector Output
Programmable standby mode (SB1, SB2 and SBR) Standby mode is controlled by three control bits of SB1, SB2 and SBR. The standby control of channel 1 and channel 2 can be made by SB1 and SB2. The on/off of reference divider is controlled by SBR.
SB1 0 0 1 1 1 Control Bit SB2 0 1 0 1 1 SBR 0 0 0 0 1 CH1 ON ON OFF OFF OFF Standby Mode Status CH2 REF ON ON OFF ON ON ON OFF ON OFF OFF Mode Status Inter-locking CH1 locking CH2 locking REF ON Standby
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GP214D 1.4GHz DUAL PLL
Filter switch control (SW) SW terminal, for switching time constant of loop filter is controlled by "SW" bit. High lock mode and normal lock mode can be arbitrarily selected by filter switch control (SW) with the charge pump output current.
SW 0 0 0 0 1 1 1 1 Control Bits CP1 CP2 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 Mode
High Lock
Normal Lock
CRYSTAL OSCILLATOR CIRCUIT (OSCI, OSCO) AND BUFFER OUT (BO) Reference frequency input is made directly to OSCI (pin 11). Buffer output (BO, pin 9) can be used for the 2nd mixer input.
REFERENCE COUNTER
When the control bits (GC1, GC2) are "11", data is transferred from shift register into the OSC R latch which sets the divide ratio of 12-bit reference counter. The divide ratio is programmed using the bits as shown in the table below.
LSB R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 GC2 "1"
MSB GC1 "1"
Reference Counter
Group Code
Divide ratio: 2xR = 2x(3 to 4095) = 6 to 8190
Divide Ratio 3 4 4095 R12 0 0 1 R11 0 0 1 R10 0 0 1 R9 0 0 1 R8 0 0 1 R7 0 0 1 R6 0 0 1 R5 0 0 1 R4 0 0 1 R3 0 1 1 R2 1 0 1 R1 1 0 1
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GP214D 1.4GHz DUAL PLL
PROGRAMMABLE N-COUNTER, CH1 AND CH2
These counters consist of the 5-bit swallow counter, the 12-bit programmable main counter, and two modulus prescaler providing divisions of 64 and 66. The swallow counter and main counter enable to set any of 192 to 262142 divisions.
LSB MSB
Swallow counter
N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11
Main counter
N12 N13 N14 N15 N16 N17 N18 N19
N-Counter divide ratio, N Group code
CH1, "10" CH2, "01"
5-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER)
Divide ratio: 0 to 31, BA A Divide N5 Ratio (A) 0 0 1 0 31 1
N4 0 0 1
N3 0 0 1
N2 0 0 1
N1 0 1 1
12-BIT MAIN COUNTER DIVIDE RATIO (B COUNTER) Divide ratio: 3 to 4095
Divide Ratio (B) 3 4 4095 N17 0 0 1 N16 0 0 1 N15 0 0 1 N14 0 0 1 N13 0 0 1 N12 0 0 1 N11 0 0 1 N10 0 0 1 N9 0 0 1 N8 0 1 1 N7 1 0 1 N6 1 0 1
Divide ratio of channel 1 and 2 = N N = 2x(32xB+A), BA A Divide ratio: 192 to 262142
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GP214D 1.4GHz DUAL PLL
TEST CIRCUIT
Sensitivity measurement - RF signal input is to be matched to 50Ohm and short line is recommended. - R1 and R2 (51Ohm) are connected to GND. - Tests at different bias and power levels are normally conducted. - Turn on DC voltage and RF signal before the data programming. - Frequency is monitored from TP1 (test point, 1) via frequency counter or oscilloscope.
Charge pump current measurement - VCP can be fixed to 1/2 VCC or varied from 0 to maximum VCC. - Charge pump polarity is changed from normal to reverse.
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GP214D 1.4GHz DUAL PLL
APPLICATION CIRCUIT
- R3~R6 & C1~C6: Loop filter components (depending on frequency, phase noise and lock time) - SW turns on when R7 is connected.
PACKAGE DEMENSIONS
16-pin TSSOP
(Unit: Millimeters)
Version 1.2 (Jan. 2006)
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GP214D 1.4GHz DUAL PLL
Version 1.2 (Jan. 2006)
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GP214D 1.4GHz DUAL PLL
Version 1.2 (Jan. 2006)
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GAINTECH INCORPORATED
GP214D 1.4GHz DUAL PLL
Version 1.2 (Jan. 2006)
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GP214D 1.4GHz DUAL PLL
Version 1.2 (Jan. 2006)
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GAINTECH INCORPORATED

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